NXP Semiconductors /MIMXRT1021 /USDHC1 /VEND_SPEC2

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Interpret as VEND_SPEC2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CARD_INT_D3_TEST_0)CARD_INT_D3_TEST 0 (TUNING_8bit_EN)TUNING_8bit_EN 0 (TUNING_1bit_EN)TUNING_1bit_EN 0 (TUNING_CMD_EN_0)TUNING_CMD_EN 0 (ACMD23_ARGU2_EN_0)ACMD23_ARGU2_EN

CARD_INT_D3_TEST=CARD_INT_D3_TEST_0, ACMD23_ARGU2_EN=ACMD23_ARGU2_EN_0, TUNING_CMD_EN=TUNING_CMD_EN_0

Description

Vendor Specific 2 Register

Fields

CARD_INT_D3_TEST

Card interrupt detection test

0 (CARD_INT_D3_TEST_0): Check the card interrupt only when DATA3 is high.

1 (CARD_INT_D3_TEST_1): Check the card interrupt by ignoring the status of DATA3.

TUNING_8bit_EN

Tuning 8bit enable

TUNING_1bit_EN

Tuning 1bit enable

TUNING_CMD_EN

Tuning command enable

0 (TUNING_CMD_EN_0): Auto tuning circuit does not check the CMD line.

1 (TUNING_CMD_EN_1): Auto tuning circuit checks the CMD line.

ACMD23_ARGU2_EN

Argument2 register enable for ACMD23

0 (ACMD23_ARGU2_EN_0): Disable

1 (ACMD23_ARGU2_EN_1): Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled.

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